This invention relates to electronic timing circuits and, more particularly, to pulse generation circuits for providing output pulse signals which occur some predetermined time interval after the applied input pulse signals.
There are numerous applications in which it is either necessary or desirable to delay an applied signal. For example, in circuits which perform a plurality of operations in a predetermined time sequence in response to a single input signal a plurality of timer circuits has heretofore most often been utilized to insure that each operation occurs at a predetermined time interval after application of the input signal. In many applications it is also necessary, in addition to delaying operation of a function, to delay termination of that function. For example, it may be necessary to delay enabling a particular relay for a predetermined interval after application of an input pulse signal and also to delay disabling or releasing the relay by a similar or different predetermined time interval after the input pulse signal has terminated.
Many circuits are known which introduce time delays to applied signals. These circuits vary in complexity from the simple monostable multivibrator to more complex circuit arrangements which precisely generate a plurality of delayed signals. In applications requiring both an operate and release delay, it has been common practice to employ a separate timer for generating each desired delay. Consequently, both circuit complexity and cost are thereby increased. Another limitation of many known timer circuits is the inability to maintain the desired timing sequence when an applied input signal is momentarily interrupted because of spurious discontinuities, i.e., noise or the like.
One analog timer circuit which has been advantageously utilized to overcome limitations of prior art timers is disclosed in U.S. Pat. No. 3,889,197 issued to T. G. Duff on June 10, 1975. An operational amplifier integrator and a voltage comparator are interconnected to realize the analog timing circuit. Basically, the integrator integrates an applied input signal while the comparator detects the voltage at an inverting input of the integrator and switches the timer output voltage in response to changes in the "virtual ground" potential at the inverting input. That is, once the integrator amplifier has reached saturation potential, the inverting input potential deviates from virtual ground. The comparator threshold voltage is adjusted so that it responds to deviations in the potential at the inverter input. Desired time delays are obtained by setting the time constant of the integrator to yield corresponding integration rates. Some degree of insensitivity to spurious discontinuities, i.e., gaps, breaks or the like, in an applied signal is realized in certain applications in which the integrator integration rate is the same for both positive and negative input signals. Although this prior known timer is somewhat insensitive to spurious discontinuities in the applied input signal, problems arise in applications in which it is desirable to have unequal operate and release delay intervals and also in certain applications including equal operate and delay time intervals. For example, in one known application, it is important that the timer recover to an initial state rapidly upon "timing-out," i.e., once the applied signal is terminated. The desired operate and recovery intervals are realized by employing first and second integration rates, respectively. The first integration rate is effective during application of an applied signal, for example, a positive input and the second integration rate is effective during absence of the applied signal, for example, a negative input. When such first and second integration rates are employed in the timer disclosed in U.S. Pat. No. 3,889,197, breaks or gaps caused by noise or the like in the applied signal cause sharp discontinuities in a ramp signal developed by the integrator. Indeed, the rapid recovery rate employed in the prior timer may even cause the ramp signal developed by the integrator to return repetitively to an initial amplitude level. Consequently, the integrator output may never reach saturation potential and, hence, the comparator output would remain unchanged thereby not yielding an indication of the presence of an applied signal. Moreover, even if the integrator output does reach the desired saturation level, the resultant pulse output from the comparator will be substantially distorted both in pulse position and pulse width.
In another known application, it is desirable to have substantially equal operate and release delay intervals. The equal operate and release intervals are obtained in the prior timer by employing equal operate and recovery integration rates. Here again, breaks or gaps near the leading and trailing edges of an applied signal cause the prior analog timer to yield a pulse signal including pulse position and pulse width errors. These errors are again caused by the operate and recover time constants of the integrator circuit.